The invention relates to digital signal sequencing circuits. More particularly, the invention relates to an unclocked digital signal sequencer having flexibly ordered output signal edges.
As integrated circuits (ICs) evolve, operating speeds are continually increasing. Therefore, the amount of time available for exchanging data between different ICs is growing ever shorter. In order to achieve a robust IC, circuit designers must take into account the following issues.
Firstly, race conditions sometimes occur, where two or more signals are xe2x80x9cracingxe2x80x9d to arrive at a common destination, e.g., the input terminals of a given circuit. The destination circuit may be designed under the assumption that the signals will arrive at the input terminals of the circuit in a certain order. (While this design technique is preferably avoided, sometimes allowing a race condition can improve the overall performance of the circuit.) However, under some manufacturing or operating conditions, the supposedly xe2x80x9cslowerxe2x80x9d signal can actually win the race, i.e., arrive prior to the supposedly xe2x80x9cfasterxe2x80x9d signal. Some of these conditions include extreme processing corners, temperatures, and power high voltage values. When such a signal reversal occurs, a temporary glitch can appear in an internal signal or an output signal of the circuit. When the circuit is a state machine, for example, a signal glitch can send the entire state machine into a wrong state.
Secondly, sometimes pulses or edges on control signals must occur in a particular order for a circuit to function properly. For example, consider a circuit that exchanges data stored in blocks A and B. First, the data from block A is latched in a temporary latch. Second, the data from block B is stored in block A. Third, the data from the temporary latch is stored in block B. These three steps must occur in this precise order, or data is lost. This order may be ensured, for example, by providing three enable signals that can only occur in the proper order.
A clock signal is often used to ensure that signals become active in a particular sequence. For example, FIG. 1A shows a simple sequencer circuit that uses a clock to produce three sequential signals that can be used as sequential enable signals. Sequencer circuit 100 includes three flip-flops 101-103 connected in series and having outputs A1-A3, respectively. The flip-flops are reset by a reset signal RST and clocked by a clock signal CK. The input DIN to the first flip-flop in the series (101) is created by ANDing (in AND-gate 111) an enable signal EN with the inverted output of flip-flop 101, inverted by inverter 112.
FIG. 1B is a timing diagram for sequencer circuit 100 of FIG. 1A. While reset signal RST is high, the three flip-flops are reset and the three flip-flop output signals are all held low. When reset signal RST is low and enable signal EN goes high, input signal DIN goes high (time T1). On the next rising edge of clock signal CK (time T2), the output signal A1 of the first flip-flop 101 goes high. Signal A1 feeds back through inverter 112 and AND-gate 111 and flip-flop input signal DIN goes low. At the next rising edge of clock signal CK (time T3), flip-flop output signal A1 goes low in response to the low value on signal DIN, while flip-flop output signal A2 goes high. At the next rising edge of clock signal CK (time T4), flip-flop output signal A2 goes low and flip-flop output signal A3 goes high. At the next rising edge of clock signal CK (time T5), flip-flop output signal A3 goes low.
While quite reliable, clock sequencer circuit 100 of FIG. 1A cannot be used for all circuits and applications. The delay between sequencer output signals A1-A3 is necessarily limited by the speed of the available clock signal CK, which can materially slow the operation of the circuit controlled by the sequencer output signals. Also, at times there is no reliable clock signal available, for example, during an IC power up sequence. An IC power up sequence includes many steps that must be performed in a predetermined sequence. However, during the earlier steps the power high level can be below that required for generating a reliable clock.
This situation can be exacerbated in a programmable logic device, where clock signals are generally routed using programmable routing resources. These programmable routing resources cannot route a clock signal until the power ramps up sufficiently to reliably configure the device. Therefore, a programmable logic device might have to provide a separate and non-programmable clock signal to control the power-up sequence.
Even in non-programmable devices, if a clock is used to control the power-up sequence additional loading is added to the clock circuitry. Because clock speed is frequently a gating item in IC design, additional loading of the clock signals is to be avoided.
Additionally, the various circuits in a device are preferably powered up at the same time. If a clocked sequencing circuit is used to control the power up sequence, the skew on the clock signal between the various circuits must be taken into account and preferably neutralized.
Therefore, unclocked sequencing circuits are sometimes used, e.g., for controlling power up sequences. FIG. 2A shows a known unclocked sequencing circuit.
Sequencing circuit 200 is a simple delay chain that includes five inverters 201-205 coupled in series. The output of the first inverter 201 provides output signal B1. The output of the third inverter 203 provides output signal B2. The output of the fifth inverter 205 provides output signal B3.
FIG. 2B is a timing diagram for sequencer circuit 200 of FIG. 2A. There are two inverters between each pair of output signals, so when input signal IN goes low, each of output signals B1-B3 goes high in turn. The sequence of the rising edges on signals B1-B3 is guaranteed.
However, there are some drawbacks to this circuit as well. As is clearly shown in FIG. 2B, the output signals occur in a set order, and with set delays between the output signals.
FIG. 3A shows a third known sequencer circuit 300 that uses inverters with different trip points to generate output signals at various points of a changing edge of an input signal. By using three inverters with different triggering voltage levels, a slow input signal SIN is detected at three different points in the leading edge of the input signal. These three different points determine the sequence in which the output signals change state.
Sequencer circuit 300 includes inverters 301, 311-313, and TP1-TP3. Input signal IN is inverted by slow inverter 301 to provide slow input signal SIN. Slow input signal SIN is monitored by inverters TP1-TP3, each of which trips at a different point on the leading edge of a pulse in slow input signal SIN. The outputs of inverters TP1-TP3 are optionally inverted by inverters 311-313, respectively, to provide sequential output signals C1-C3.
FIG. 3B is a timing diagram for sequencer circuit 300 of FIG. 3A. When input signal IN goes low, slow inverter 301 starts to change state. Gradually, slow input signal SIN rises. At time t1, inverter TP1 is tripped, causing output signal C1 to go high. At time t2, slow input signal SIN has risen to the point where inverter TP2 is tripped, and output signal C2 goes high. Similarly, at time t3, inverter TP3 is tripped and output signal C3 goes high.
When input signal IN goes high again, slow input signal SIN gradually falls. As signal SIN falls back past the trip points of the three inverters TP1-TP3, their respective output signals return to the low state in reverse sequence.
A limitation to prior art unclocked sequencer circuits, including those shown in FIGS. 2A and 3A, is that gates in the circuit must be carefully sized, while processing, operating temperature, and the power high level must all be carefully controlled for the circuits to function predictably. If changes are made in any of these factors, or in the circuits controlled by a sequencing circuit (e.g., altering the loading of the sequencer output signals), then the sequencer circuit must be resimulated. Often, changes must be made to adapt the circuit to the new conditions.
A limitation common to all of the sequencing circuits previously described is that the order of the trailing edges on the output signals is fixed. For example, in the circuits of FIGS. 1A and 2A, the order of the trailing edges is always the same as the order of the leading edges. In the circuit of FIG. 3A, the order of the trailing edges is the reverse of the order of the leading edges. A sequencing circuit would be much more flexible if the leading and trailing edges of the output signals could occur independently and in any order. For example, given that capability, events controlled by the sequencer output signals could be made either completely sequential or concurrent (overlapping).
It is desirable to provide a sequencer circuit that addresses one or more of the limitations described above.
The invention provides an unclocked, digital sequencer circuit having flexibly ordered leading and trailing edges on the output signals. The sequencer circuit of the invention includes a dual-input latch that detects only leading edges on a first input terminal and only trailing edges on a second input terminal. A third input terminal provides a triggering input signal. When the triggering input signal is in one state (e.g., low), all trailing edges are ignored. When the triggering input signal changes state (e.g., goes high), the next leading edge (e.g., the next high edge) on the first input terminal is detected and changes the state of the dual-input latch. The next trailing edge (e.g., the next falling edge) on the second input terminal is then detected and returns the dual-input latch to its previous state.
One embodiment of the invention also includes a delay line, e.g., a series of inverters coupled in series. The triggering input signal drives the first inverter, while alternating inverters in the series (e.g., the second, fourth, and sixth inverters) provide successively delayed input signals. Two of these delayed input signals are coupled to the first and second input terminals of each of two or more dual-input latches. The output terminals of the dual-input latches provide a set of sequencer output signals. The order of the output signal edges depends on which delayed input signals are selected to drive each dual-input latch. The order of the leading edges can be made different from the order of the trailing edges simply by using appropriately delayed input signals to drive the first and second terminals of the dual-input latches.
Some embodiments of the invention use high pulses on the input and output signals. In other words, a leading edge is detected when the input signal transitions from low to high, and a trailing edge is detected when the input signal transitions from high to low. In one such embodiment, the dual-input latch is implemented using three NAND gates. Two of the NAND gates are cross-coupled. Of these two NAND gates, a first NAND gate provides the sequencer output signal and is also driven by a third NAND gate NANDing the triggering input signal with a signal from the first input terminal. The second cross-coupled NAND gate is also driven by a signal from the second input terminal. In other embodiments, other implementations of the dual-input latch are used to detect and generate high pulses.
Other embodiments of the invention use low pulses on the input and output signals. In other words, a leading edge is detected when the input signal transitions from high to low, and a trailing edge is detected when the input signal transitions from low to high. In one such embodiment, a dual-input latch is implemented using NOR gates. The latch is otherwise similar to the NAND gate latch described above. In other embodiments, other implementations of the dual-input latch are used to detect and generate low pulses.
In one embodiment, the selection of delayed input signals applied to the first and second input terminals of the dual-input latches is programmable. Thus, the sequence of the output signals is programmable. Further, the sequence of the leading edges is programmable, and the sequence of the trailing edges is independently programmable. This embodiment is particularly applicable to programmable logic devices, but is not limited thereto.